Design and Implementation of Serializer/Deserializer (SerDes) For triple Speed Ethernet (MAC) Vandhana S.1, Marjorie Roji1, Niranjana S.1 1Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha University, Thandalam, Chennai Mathematics Subject Classification: 94B35, 94B99, Computing Classification System: B.6, B.7 Online published on 16 January, 2018. Abstract A Serializer/Deserializer (SerDes) is commonly used in high speed communications to reduce the number of input/output pins and their interconnections. The use of SerDes is to convert the parallel data into serial data and vice versa. Serial transmission is used here to minimize the cost and increase the performance and data rate, hence Ser Des is the right choice. Here, we design and implement SerDes for triple speed ethernet MAC. The designing is done using Quartus II software while it is implemented on FPGA board using Cyclone IV E device. Top Keywords Triple Speed Ethernet (TSE) MAC, Serial data transmission, 8b/10b encoder/decoder, SerDes, FPGA. Top |